1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a P-channel transistor to which a well voltage is applied.
2. Description of the Related Art
In semiconductor memory devices, a control circuit controlling memory cells is formed around the memory cells. The control circuit comprises elements such as a transistor or diode. For example, the control circuit is composed of a P-channel transistor 40 shown in FIG. 5. The P-channel transistor 40 is formed in a substrate or well formed in the substrate, and supplied with well voltage (back gate voltage) VB in addition to gate voltage VG, source voltage VS and drain voltage VD. The Source voltage VS is supplied from a first power supply and it is a power supply potential Vcc. The Well voltage VB is supplied from a second power supply formed of a charge-pump circuit in the semiconductor memory device, and it is usually a boosted potential Vpp. That is, VB=Vpp≧VS=Vcc.
As illustrated in FIG. 6, the P-channel transistor 40 comprises first semiconductor region 51, P-type second semiconductor regions 52, 53, and gate electrode 54. The first semiconductor region 51 is formed of an N-type well or N-type semiconductor substrate. The P-type second semiconductor regions 52 and 53 are formed in the first semiconductor region 51, and constitute source and drain regions of the P-channel transistor 40. The gate electrode 54 is formed on the first semiconductor region 51 via a gate insulating film. The gate electrode 54, second semiconductor regions 52, 53 and first semiconductor regions 51 are supplied with gate voltage VG, source voltage VS, drain voltage VD and well voltage VB, respectively.
JPN. PAT. APPLN. KOKAI Publication No. 7-131332 is given as the document relevant to a CMOS circuit having the following structure. According to the structure, P-channel and N-channel MOS transistors are connected in series, and the node between both MOS transistors is used as an output terminal. In FIG. 1 of the foregoing publication, there is shown a circuit, which blocks a reverse current from the output side so that undesired current cannot be carried.
FIG. 5 and FIG. 6 are a circuit diagram and cross-sectional view showing a conventional semi-conductor device. In a P-channel transistor 40, well voltage VB is usually set to a voltage higher than source voltage VS. However, if many cells are operated and a large current flows through a power supply supplying boosted potential Vpp, the boosted potential falls; for this reason, the well voltage VB becomes lower than the source voltage VS. In addition, when noise is generated, the boosted potential falls; for this reason, the well voltage VB becomes lower than the source voltage VS. When the potential of the boosted potential falls and the well voltage VB becomes lower than the source voltage VS by the threshold value of the PN junction between source and well, the PN junction between source and well is forward-biased; therefore, it turns on. As seen from the arrows shown in FIG. 6, a large numbers of carriers are generated in a substrate. For this reason, there is a problem that a parasitic transistor comprising substrate, source and well latches up, and large current flows therethrough.